The present invention relates to semiconductor device manufacturing, and more particularly to a method of fabricating a dual workfunction metal oxide semiconductor field effect transistor (MOSFET) in which the problem of defining dual workfunction gate doping is solved, while providing contacts to the source/drain diffusions which are borderless to the gate conductors. The dual workfunction MOSFETs of the present invention can be used for high-performance memory applications such as embedded dynamic random access memory (DRAM) cells.
In the field of semiconductor device manufacturing, MOSFETs having borderless contacts are generally fabricated by forming a gate stack that is capped with an insulator on a surface of a semiconductor substrate and then defining the gate conductors by etching through all the layers of the gate stack. Such a process is amendable for forming N+ doped gate conductors wherein the gate doping is provided prior to the formation of the insulating cap. In order to provide dual workfunction doping on a selective basis, the insulating layer over the gate stack must be selectively removed from the support regions of the device. This requires an additional masking step to block regions wherein the insulating cap is desired to be retained for the formation of borderless diffusion contacts in the array. Therefore, typical prior art processes do not allow dual workfunction gates with borderless contacts in the support regions.
FIG. 1 shows a prior art structure which is formed utilizing the above-mentioned prior art process. Specifically, FIG. 1 shows a structure comprising semiconductor substrate 10 having patterned gate dielectric 12 formed thereon. On top of portions of gate dielectric 12 are gate stacks 14 which each include lower conductive portion 16 and upper insulating portion 22. The lower conductive portion comprises N+ polysilicon region 18 and refractory metal silicide region 20. An optional barrier layer (not shown) may be present between regions 18 and 20. Spacers 24 are formed on exposed sidewalls of each gate stack and on top of gate dielectric 12. Borderless diffusion contact 26 is formed between adjacent gate stacks so as to contact one of the diffusion regions (labeled as 28 in FIG. 1) which is present in semiconductor substrate 10.
Specifically, the prior art structure of FIG. 1 is formed by first depositing conductive layers (i.e., N+ polysilicon and refractory metal silicide) on the gate dielectric and thereafter forming an insulating layer such as SiN on the refractory metal silicide layer prior to etching the gate stack. Following the formation of the insulating spacers, a contact to one of the diffusion regions of the MOSFET which overlaps the gate conductor may be formed. The structure shown in FIG. 1 as well as the method that is employed in fabricating the same is commonly employed in current DRAM technology wherein a single-gate workfunction is used (i.e., buried-channel PMOSFETs) with borderless diffusion contacts in the array.
As stated above, the prior art process requires predoping of the gate conductor in the array, while blocking the supports if dual workfunction is required. Dual workfunction gate doping in the supports (without any borderless contacts) is achieved by selective removal of the insulating cap followed by doping of the gate conductor. Thus, in the prior art, application of two block masks are required to fabricate dual workfunction MOSFETs in the support regions; (1) for blocking the array gate doping from the supports; and (2) for blocking the array during removal of the insulating gate cap from the supports.
With decreasing groundrules, scalability of the channel length of buried-channel PFET is severely limited by short-channel effects (i.e., the decrease of threshold voltage in short-channel devices caused by two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions). This requires the use of dual workfunction (i.e., surface channel) MOSFETs, while allowing the formation of borderless contacts in the array. The need for dual workfunction MOSFETs with borderless diffusion contacts is of utmost importance for high-performance logic containing high-density DRAMs.
U.S. Pat. No. 5,937,289 to Bronner, et al. discloses a process for providing dual workfunction gates, each gate having a self-aligned insulating top layer. In the xe2x88x92289 patent, the entire gate stack is formed prior to etching and doping is introduced into the etched gate stack through the sidewalls thereof.
U.S. application Ser. No. 09/325,941, filed Jun. 4, 1999 provides a method for fabricating dual workfunction gates wherein each gate has a self-aligned insulating top layer. In the ""941 application, the entire gate stack is defined before etching and doping occurs through ledges that are present on partially etched gate stacks.
Despite the processes described in the prior art, there is a continued need of providing a method that solves the problem of defining dual workfunction gate doping, while providing contacts to the source/drain diffusion regions which are borderless to the gate conductor. As such, a method which is capable of solving the above-mentioned problem is required and would represent a significant advancement in the field of semiconductor device manufacturing.
One object of the present invention is to provide a method of fabricating a dual workfunction MOSFET.
Another object of the present invention is to provide a method of fabricating a dual workfunction MOSFET in which borderless diffusion contacts are present in both the array and support device regions of the integrated semiconductor structure.
A still further object of the present invention is to provide a method of fabricating a dual workfunction MOSFET wherein the gate conductors are defined and doped prior to the formation of an insulating cap thereon.
A yet further object of the present invention is to provide a method of fabricating a dual workfunction MOSFET with borderless diffusion contacts in which the two block masks required in prior art processes are eliminated thereby reducing the cost of manufacturing the same.
An even further object of the present invention is to provide a method of fabricating a dual workfunction MOSFET with borderless diffusion contacts wherein the height of the gate stack is reduced thereby improving the width-tolerance of the gate conductor.
An additional object of the present invention is to provide a method of fabricating a dual workfunction MOSFET with borderless diffusion contacts in which the device has reduced capacitance relative to prior art devices.
These and other objects and advantages are achieved in the present invention by employing a method wherein a self-aligned insulating gate cap is formed on top of a previously defined and doped gate conductor region. The inventive method which forms an insulating cap that is self-aligned to an underlying gate conductor enables the formation of dual workfunction gate conductors and borderless diffusion contacts without the need of employing separate block masks as required by prior art processes.
Specifically, the method of the present invention comprises the steps of:
(a) providing a semiconductor structure which includes at least one array device region and at least one support device region, wherein each of said regions includes patterned polysilicon gate conductors, and salicide regions formed over at least diffusion regions that are formed in a surface of a semiconductor substrate between said patterned polysilicon gate conductors;
(b) forming a material stack on said semiconductor structure, said material stack comprising a bottom nitride layer formed on all exposed surfaces of said semiconductor structure, a polysilicon layer formed on said bottom nitride layer, and a top nitride layer formed on said polysilicon layer,
(c) forming a planarizing material on said material stack and planarizing said planarizing material so as to expose said top nitride layer that is present above said patterned polysilicon gate conductors;
(d) removing exposed portions of said top nitride layer so as to expose portions of said polysilicon layer that is present above said patterned polysilicon gate conductors;
(e) removing said planarizing material and forming an oxide region on exposed portions of said polysilicon layer that is present above said patterned polysilicon gate conductors;
(f) removing said top nitride layer and said polysilicon layer that abut said oxide region so as to expose said first nitride layer of said material stack;
(g) forming oxide spacers abutting said patterned polysilicon gate conductors;
(h) forming a third nitride layer on all exposed surfaces of said semiconductor structure;
(i) forming a planarized layer of glass material on said third nitride layer;
(j) providing an opening in said semiconductor structure between adjacent patterned polysilicon gate conductors in said at least one array device region so as to expose said salicide region formed on one of said diffusion regions; and
(k) forming a borderless diffusion contact within said opening.